Hello there, my name is Leland Chang and I am from IBM, and I'm here to talk to you all
a little bit today about voltage scaling and Vmin which is a particularly important topic
in the circuits community today because of the need for power efficiency.
So, what I hope to do in this video is give you a little bit of context as to how all
of the different components of Vmin fit together so that you might be able to design more power
efficient circuits in the future.
So, let's start with a little definition here, because Vmin is a term that's been used for
a lot of different things.
In this context we're going to assume that Vmin is the minimum supply voltage that can
be used for a given VLSI chip and of course we're going to want to use the lowest possible
voltage we can and that's because power of course is a quadratic function of voltage
but we also have to remember that we have to meet our target chip specifications and
because the performance and functionality all has to be sufficient.
Performance in particular might be a challenging one because voltage scaling is going to degrade
our transistor drive current and performance, especially with Moore's-law challenges, is
going to be an issue that we're going to need to discuss.
Functional margins are also going to be an issue we can't forget about that either because
variability and reliability are difficult challenges going forward.
So, in this video, we're going to focus on chip level Vmin, that really means we're going
to talk about digital and memory because that is what comprises most VLSI chips today.
We're not going to talk very much about analog and IO circuits, these become very specialized
and are thus beyond the scope of this discussion.
So I'm going to start with a cartoon of how all the different components of Vmin fit together.
You can see here how as we discussed we want chip functionality and performance to be acceptable
for our chip, and we all know that we're going to have some nominal voltage margin that we're
going to have to have to make sure this chip works.
Then we're going to have to apply some variability margin and some reliability margin on top
of that to make sure that we meet both metrics.
So in this cartoon, I've shown that the performance limited Vmin is a little bit higher than functionality
limited Vmin, this is going to depend on our application.
Sometimes it's going to be one, sometimes it's going to be the other.
For example, for a logic path it might be more performance limited, whereas for a memory
path it might be more functionality limited because generally memory is very sensitive
to variability.
We're going to talk about that in a later slide.
Now on top of this, we're going to need to apply a power delivery margin.
This is a little bit unusual for us chip designers to think about, but we have to remember what
we're trying to do at the end of the day is to design power efficient systems and we always
have to deliver power from the wall plug out to our chip and we're always going to incur
some amount of IR drops and L(dI/dt) noise and so when we talk about a Vmin we're going
to need to talk about all of these all together.
So we're going to talk about all of these different components, the only one we're going
to skip through a little bit is reliability and that's for the sake of time.
But, for simplicity we can think of reliability a temporal Vt variation and so we can lump
that concept in with variability.
So, let's start with performance limited Vmin.
Usually when we get ac hip out of the fab, we're going to measure the characteristics
and we're going to do a Shmoo plot like this, where we plot frequency vs. voltage.
We're going to have regions in this plot where the chip is going to work, say green boxes,
and regions where the chip is not going to work, red boxes, and we're going to have a
boundary between these two regions which will normally look like a line for most practical
chips that we get.
But, based on this boundary, we're basically going to be able to figure out where the Vmin
is, we're going to just read it off, because for a given frequency target here, there is
going to be a minimum voltage at which we meet that performance and so this is going
to be the Vmin for a single chip.
And there's probably not too much we're going to talk about in this video to try to improve
this particular single chip because you have a fixed function, you're a great circuit designer
so you've probably already done really well there.
What we're going to talk more about is populations of chips and how we deal with that.
That's because variability is obviously a very big concern for us these days and we
know that when we get chips back out of the fab there's going to be a distribution of
characteristics.
There's going to be a worst case chip, which for performance limited Vmin is going to be
the slowest chip and that boundary line that we saw in the previous chart is probably going
to move higher here such that we're going to have a higher Vmin for this worst case
chip.
So as a circuit designer what we're probably going to focus on is trying to improve this
performance limited Vmin by either minimizing our transistor variability, trying to stop
the problem at the source.
For example, we can use wider transistors that vary less or we can use a lower Vt on
these transistors such that the gate overdrive does not get degraded when we have variability.
So, we're obviously going to incur some trade-offs here because of capacitance and maybe leakage
but it will allow us to achieve a lower Vmin which is what we're trying to do, push this
curve lower.
The other thing that we can try to do is to minimize the circuit variability margin that
we have to apply to tolerate lots of variation.
We're just going to get what we get and then we're going to shave the margin as small as
we can.
People have proposed a lot of ways to do this with critical path timing monitors or maybe
asynchronous circuits all focusing on brining that margin as small as we can so that the
Vmin that we actually realize on the chip can be as close to the nominal as possible
so that Vmin can actually be improved.
So, speaking of variability we're going to talk a little bit more now about functionality-limited
Vmin, in particular we're going to focus on SRAM.
And this is because variability is probably much more important in this case than the
performance-limited Vmin that we just discussed.
SRAM Vmin has been a very hot topic in the research world in recent years because SRAM
is so incredibly limited by random variation.
This is because there's sort of a perfect storm, of a couple of issues coming together
to really make SRAM Vmin very difficult to optimize.
First, is because SRAM is generally made out of the smallest transistors on the chip and
you have very high Vt in this device to try to keep the leakage down.
But that leads to very large random variation, the sigma-Vt that you might see, this is based
on statistical dopant fluctuation modeling.
You can see that a small device with small dimensions and a high doping concentration
is going to lead to a very large sigma-Vt.
So you're going to get a lot of variation in your transistors to begin with but what
makes it worse is that the cell operation of your traditional 6T SRAM cell is very sensitive
to the transistor strength ratios.
That's because we use the same devices for both the read and the write operations, it's
these pass gate devices right here.
And you can imagine that you want them to be incredibly strong to write the cell, but
then you don't want them to be too strong when you read the cell because you don't want
to accidentally write to the cell.
And so you can image that there must be a delicate balance that you have to preserve,
and once you have variability, this is going to be a challenge.
And finally, statistics are not in your favor because on a given VLSI chip these days, you
might have many megabytes of SRAM and then you have to think about the tails of the distribution
out to five, six sigma, everything has to work.
You also don't get any averaging, if you're talking about random variation for say a logic
path, then each successive stage is going to average out the random variation a little
bit.
But in an SRAM cell you've got to access that cell, it's got to work and so this is going
to be very challenging.
So as I mentioned, the SRAM guys in the world have worked very hard on this problem over
the last several years, tried all kinds of different solutions.
Most of the most effective ones have boiled down to just this, we focus on the peripheral
circuits, we try to do read and write assist circuits.
So we tune the cell as much as we can and then we focus on the peripherals and try to
increase the margins as much as we can beyond that.
And so what we're trying to do in all these cases is some type of dynamic modulation of
the device strengths.
So we'll play with the bit-line and word-line voltages, we'll create new voltages locally,
that are say between zero and VDD or maybe even outside, higher or lower.
And we're going to try to drive the different devices, either more weakly or more strongly
to try to get more read vs. write operating margin.
And so, this is going to decouple the read vs. write operations and thus buy us a lot
of Vmin.
For high-performance applications we may not be willing to do some of these techniques
because these you could imagine, might incur some timing penalty.
You're trying to generate these voltages, there's some pulsing, some capacitive boosting
involved very often, and so there we might use dual supplies, we might use explicit supply
voltages for this.
We may even add some extra transistors to this cell to try to really decouple the read
and the write.
So now I want to talk a little bit about power delivery.
As I said, we are chip designers but we do have to think about the end product and when
we talk about Vmin, this is particularly important because when we look at Vmin, it could be
different whether we're talking about Vmin at the circuit, out at the C4s or maybe out
at the voltage regulator module. because we have parasitics out on the board and the package
and the back end, there are are IR drops and there are L(dI/dt)'s going on everywhere.
And, this is going to be challenging especially at low voltage because if we fix the power
then currents is going to go up and obviously IR and L(dI/dt) are all going to go up as
well.
So this is definitely something we have to think about when we're thinking about Vmin
and how we're defining Vmin even.
As a circuit designer what we're now going to need to think about is trying to improve
the margins for both IR and L(dI/dt).
Decoupling capacitance is the passive way of doing this, to try to improve the L(dI/dt)
margin, we might try to add dedicated structures on the chip to put a lot of capacitance there.
We might put say linear regulators to add active Vdd regulation, to compensate some
of the L(dI/dt) drops.
Or a more exotic technique which is actually becoming much more practical these days is
trying to deliver our power, through all our parasitics, at a high voltage.
So, we keep it at a high voltage here, so the current levels are lower and then we bring
it to the chip.
And what we have to do on the chip now is step that voltage down to the actual Vdd that
we want.
But, this can help to mitigate the margins that we have to apply.
So, I want to finish this video with a little discussion on how our jobs as circuit designers
are going to relate to our friends over on the technology side of things and also our
friends over on the system architecture side of things.
First, with technology, obviously we all know that technology progresses very quickly, there
are new things going on all the time.
For example, one of the big things these days is FinFET, starting at the 22nm node, going
to 16nm and 14nm, this is what everyone is using.
It brings some very interesting things that helps us with Vmin, also some challenges as
well.
The structure itself is quite wonderful for gate length scaling with low channel doping.
So you can imagine that that better scaled device is going to be higher current at low
Vdd.
It's going to have lower sigma-Vt because of the channel doping.
These are going to be good things for Vmin.
But, at the same time, it's a vertical structure, it's quantized when you want to change the
fin width.
You can only put two fins, three fins, integer numbers of fins.
The vertical structure is going to lead to a very strong PFET drive strength.
And so these two issues together are actually going to limit your SRAM tuning capability
a little bit and so that's actually going to hurt your Vmin in that case.
So, you're going to get some pluses, you're going to get some minuses; the pluses probably
outweigh the minuses, but there's a little trade-off and we're going to have to understand
as circuit designers what we're going to have to really focus on.
The other thing we're going to have to remember is that the technology guys will always improve
process control, variability is going to get better and better as time goes on.
Ideas like directed self-assembly, that are pretty exotic, may sometime come into play
and thus we will probably be able to improve our Vmin just from these types of ideas.
So the thing to remember, the issues that we've discussed, the solutions we've discussed
so far, they will probably always be needed, because we're always going to want to get
the lowest voltage we can possible.
But, we should keep in mind that the technology progress will, for the most part, help to
improve Vmin.
So finally, I want to say a few words about application dependencies, because while all
the issues we've discussed in this video are probably common to any application, you're
always going to need to worry about performance and functionality and power delivery.
But, whether you're talking about a low-power, lost-cost part, or a high-performance-part
that you're trying to build at the end of the day, the trade-offs and the key issues
that you need to be very good at are all going to be very different.
And so really, at the end of the day, you want to know what different Vmin solution
options you have out there, and you're probably going to choose different ones whether you're
in one camp or the other.
So, just to summarize, I hope I've convinced you that understanding Vmin is very important
in power efficiency for VLSI design today.
We've talked a little bit about performance and functionality limits and we've talked
about how variability and reliability margins come into play.
We've also talked about power delivery.
So, beyond the Chip itself, the system is really what we want to think about.
So there's lots for us as designers to do.
We really need to remember to talk to our technology friends and our application system
designer friends to understand how technology is going to evolve as well as how customer
needs are going to evolve in the future.
Thank you very much.
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